Averant's Property Verification Gears up for Mainstream
SANTA CLARA, Calif.--(BUSINESS WIRE)--May 8, 2002--Averant, Inc. a
leading provider of static functional verification and property
checking software for RTL level Verilog and VHDL designs, today
announced that Solidify(TM), its flagship functional verification
product has been put into production use by more than 27 companies
worldwide. Averant's customers include leading companies designing
ICs, ASICs, and FPGAs for telecommunication, networking, and data
processing applications.
Solidify's property verification solution has been successfully
adopted by these customers to find and fix functional errors early in
the design cycle and significantly reducing the time to verify while
increasing the quality of verification.
Solidify's earliest success came through Averant's collaboration
with designers and verification engineers at companies like Cisco
Systems, Compaq Computer, Nvidia, UltimateTV, Lucent, Hitachi and
Fujitsu. RTL blocks that could not be thoroughly verified using
simulation were exhaustively verified using Solidify.
"We determined it is crucially important to accelerate functional
verification to keep our aggressive projects on schedule. We expect
that by using Solidify we will not only shorten our verification
schedules, but also improve our quality of results," said Chris
Malachowsky, Vice President of Engineering, NVIDIA. "Rising levels of
integration significantly increases the likelihood a bug hiding in a
block may not be found. These bugs are difficult to find and costly to
fix at the chip-level. The use of Solidify's static verification, at
the block-level before integration, will enable us to find corner
cases that were previously too difficult or too time-consuming to
reach".
"Compaq has adopted a new methodology called static functional
verification to attack difficult problems that demand significant
design process bandwidth and are costly," Said Paul Rawlins, Senior
Technical Staff, Compaq Computer. "Static functional verification
allows a designer to completely verify the operation of a design
without having to establish a verification testbench or develop
simulation vector patterns. Instead, static functional verification
uses a set of properties that describe the behavior of the design to
prove proper functionality using formal verification techniques."
In Japan, Solidify was put in a widespread use. Averant's
exclusive distribution relationship with SC Hightech has led to a
rapid market acceptance. Within 6 months of introduction, Solidify was
evaluated and purchased by Hitachi, Fujitsu, Toshiba, NEC, Matsushita,
EPSON, and STARC. These companies utilize Solidify extensively and
have discovered that Solidify improves design quality while reducing
time-to-market.
"Solidify uses a Verilog-like property language, making it is easy
for designers to understand and write properties," said Toshiyuki
Igarashi, Manager for Fujitsu's MCU Technology Dept. System Micro
Division. "We are developing a methodology to write effective
properties and will broadly adopt this methodology for our MCU
products in various applications. We aim to eliminate time-consuming
vector based logic simulation for many design blocks, using Solidify
to achieve high quality verification in a short time."
Solidify was also purchased by new and upcoming networking and
telecommunication start-ups like Tau Networks, Lynx Photonic Networks,
Lenslet Labs, and Terago Communication where it has proved to be a
productive verification solution that provides a competitive
advantage.
"Formal verification's main strength is that unlike simulation, it
does not depend on the probability of reaching any given scenario. If
the scenario can occur, however infrequently, formal verification will
find it," said Elchanan Rappaport, Logic Development Manager, Lynx
Photonic Networks. "This makes the difference for complex systems
where the number of degrees of freedom makes it impossible to design a
simulation environment which will not miss certain combinations. In
fact, we have found a number of just such bugs in designs we had
thought were exhaustively simulated, by using Solidify."
Enhanced usability, increased performance, quick debugging
capacities, and extensions to Solidify's property language prompted
ARM, LSI Logic, AMD, Agilent, Qlogic, Tellabs, and other major
semiconductor and networking companies to purchase Solidify. Combined
with system-level simulation and other traditional verification
methods, these companies use Solidify to formally verify designs as
early as possible and prior to integration.
"Using Solidify, the unit-level verification of a wireless
networking product is drastically reduced to half," said Rex Hsueh, a
project lead at AMD wireless networking group. "Solidify surprisingly
uncovered several architecture corner case bugs that could have turned
into potential system bugs. Design properties are easy to create and
maintain, and Solidify provides quick feedback when properties fail."
"ARM uses many different validation techniques, including formal
verification, to ensure high quality CPU cores. The exhaustive nature
of formal verification makes it ideal for verifying every possible
corner case -- essential for configurable IP that's used by many
customers in a variety of environments," said Mike Turpin, Principal
Validation Engineer at ARM. "We've recently had success with the
Solidify property checker from Averant, using its verilog-like
property language to find and fix bugs in CPU blocks and interfaces.
It can also extract a few standard properties directly from the RTL,
allowing certain bugs to be found quickly and efficiently."
"EDA industry is experiencing a tremendous growth by creating new
design and verification technologies to benefit a broad range of
applications," said Behrooz Zahiri, vice president of Marketing for
Averant. "We're extremely pleased with the diversity of customers
using Solidify and the breadth of verification problems solved by
Solidify. We have learned from each customer, and continuous
improvements have made Solidify a practical functional verification
tool for today's VHDL and Verilog designs."
About Averant
Averant, Inc., founded in 1997, is a privately held EDA company
leading the emerging market for static functional verification and
property checking. Averant develops, sells, and supports worldwide
Solidify, a software tool that delivers unprecedented performance in
verification of HDL designs. Solidify improves verification
productivity and design quality while reducing time-to-market and
schedule risk. For more information, visit Averant's web site at
www.averant.com, or contact by email at info@averant.com or by phone
at 408/844-8440.
Contact:
Averant, Inc.
Behrooz Zahiri, 408/981-4466
bzahiri@averant.com